Project Statistics |
PROP_CompxlibOverwriteLib=true |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PostTrceFastPath=false |
PROP_PreTrceFastPath=false |
PROP_PrecVhdlSyntax=VHDL 93 |
PROP_PropSpecInProjFile=Store all values |
PROP_SimModelInsertBuffersPulseSwallow=false |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_XPowerOptLoadXMLFile=changed |
PROP_XPowerOptOutputFile=changed |
PROP_intProjectCreationTimestamp=2015-08-12T12:59:39 |
PROP_intWbtProjectID=BA466B1531AB2551D295982D279652AA |
PROP_intWbtProjectIteration=2 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxSynthKeepHierarchy=Yes |
PROP_xilxSynthRegDuplication=false |
PROP_xstEquivRegRemoval=false |
PROP_xstSliceUtilRatio=97 |
PROP_AutoTop=true |
PROP_CompxlibSmartModels=true |
PROP_DevFamily=Spartan3 |
PROP_MapEffortLevel=Standard |
PROP_vsim_otherCmdLineOptions=-novopt |
PROP_CompxlibSimPath=changed |
PROP_DevDevice=xc3s4000 |
PROP_DevFamilyPMName=spartan3 |
PROP_DevPackage=fg676 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-5 |
PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
FILE_VHDL=18 |