Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.3 (ISE) - P.40xd Target Family: Spartan3
OS Platform: LIN Target Device: xc3s4000
Project ID (random number) 93f1c69b8f454213a35b2d78fcdd5897.BA466B1531AB2551D295982D279652AA.2 Target Package: fg676
Registration ID 174131719_174131720_210570364_664 Target Speed: -5
Date Generated 2015-08-12T13:12:48 Tool Flow ISE
 
User Environment
OS Name Ubuntu OS Release Ubuntu 12.04.5 LTS
CPU Name Intel(R) Core(TM)2 Duo CPU T9550 @ 2.66GHz CPU Speed 1600.000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=9
  • 105-bit adder=8
  • 4-bit adder=1
Comparators=8
  • 104-bit comparator equal=8
Counters=3
  • 4-bit up counter=2
  • 7-bit up counter=1
FSMs=3 Multiplexers=1
  • 8-bit 16-to-1 multiplexer=1
Registers=854
  • Flip-Flops=854
MiscellaneousStatistics
  • AGG_BONDED_IO=3
  • AGG_IO=3
  • AGG_SLICE=927
  • NUM_4_INPUT_LUT=996
  • NUM_BONDED_IOB=3
  • NUM_BUFGMUX=1
  • NUM_CYMUX=824
  • NUM_LUT_RT=104
  • NUM_SLICEL=927
  • NUM_SLICE_FF=881
  • NUM_XOR=832
NetStatistics
  • NumNets_Active=2232
  • NumNets_Gnd=8
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=450
  • NumNodesOfType_Active_CNTRLPIN=887
  • NumNodesOfType_Active_DOUBLE=2076
  • NumNodesOfType_Active_DUMMY=2074
  • NumNodesOfType_Active_DUMMYESC=2
  • NumNodesOfType_Active_GLOBAL=63
  • NumNodesOfType_Active_HFULLHEX=24
  • NumNodesOfType_Active_HLONG=5
  • NumNodesOfType_Active_HUNIHEX=71
  • NumNodesOfType_Active_INPUT=3375
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=1886
  • NumNodesOfType_Active_OUTPUT=2227
  • NumNodesOfType_Active_PREBXBY=1467
  • NumNodesOfType_Active_VFULLHEX=215
  • NumNodesOfType_Active_VLONG=53
  • NumNodesOfType_Active_VUNIHEX=155
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_INPUT=8
  • NumNodesOfType_Gnd_OMUX=5
  • NumNodesOfType_Gnd_OUTPUT=5
  • NumNodesOfType_Gnd_PREBXBY=8
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_VCCOUT=1
SiteStatistics
  • IOB-DIFFM=2
  • IOB-DIFFS=1
  • SLICEL-SLICEM=461
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=3
  • IOB_INBUF=2
  • IOB_OUTBUF=1
  • IOB_PAD=3
  • SLICEL=927
  • SLICEL_CYMUXF=416
  • SLICEL_CYMUXG=408
  • SLICEL_F=498
  • SLICEL_F5MUX=27
  • SLICEL_F6MUX=8
  • SLICEL_FFX=438
  • SLICEL_FFY=443
  • SLICEL_G=498
  • SLICEL_XORF=416
  • SLICEL_XORG=416
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IOB
  • O1=[O1_INV:0] [O1:1]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:1]
IOB_PAD
  • DRIVEATTRBOX=[12:1]
  • IOATTRBOX=[LVCMOS33:3]
  • SLEW=[SLOW:1]
SLICEL
  • BX=[BX_INV:1] [BX:453]
  • BY=[BY:429] [BY_INV:1]
  • CE=[CE:437] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:408]
  • CLK=[CLK:450] [CLK_INV:0]
  • SR=[SR:450] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:416] [0_INV:0]
  • 1=[1_INV:0] [1:416]
SLICEL_CYMUXG
  • 0=[0:408] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:27] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:8] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:429] [CE_INV:0]
  • CK=[CK:438] [CK_INV:0]
  • D=[D:437] [D_INV:1]
  • FFX_INIT_ATTR=[INIT0:431] [INIT1:7]
  • FFX_SR_ATTR=[SRLOW:431] [SRHIGH:7]
  • LATCH_OR_FF=[FF:438]
  • SR=[SR:438] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:438]
SLICEL_FFY
  • CE=[CE:434] [CE_INV:0]
  • CK=[CK:443] [CK_INV:0]
  • D=[D:442] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:434] [INIT1:9]
  • FFY_SR_ATTR=[SRLOW:434] [SRHIGH:9]
  • LATCH_OR_FF=[FF:443]
  • SR=[SR:443] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:443]
SLICEL_XORF
  • 1=[1_INV:0] [1:416]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IOB
  • I=2
  • O1=1
  • PAD=3
IOB_INBUF
  • IN=2
  • OUT=2
IOB_OUTBUF
  • IN=1
  • OUT=1
IOB_PAD
  • PAD=3
SLICEL
  • BX=454
  • BY=430
  • CE=437
  • CIN=408
  • CLK=450
  • COUT=408
  • F1=498
  • F2=444
  • F3=76
  • F4=27
  • F5=16
  • FXINA=8
  • FXINB=8
  • G1=498
  • G2=444
  • G3=64
  • G4=22
  • SR=450
  • X=463
  • XQ=438
  • Y=458
  • YQ=443
SLICEL_CYMUXF
  • 0=416
  • 1=416
  • OUT=416
  • S0=416
SLICEL_CYMUXG
  • 0=408
  • 1=408
  • OUT=408
  • S0=408
SLICEL_F
  • A1=498
  • A2=444
  • A3=76
  • A4=27
  • D=498
SLICEL_F5MUX
  • F=27
  • G=27
  • OUT=27
  • S0=27
SLICEL_F6MUX
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
SLICEL_FFX
  • CE=429
  • CK=438
  • D=438
  • Q=438
  • SR=438
SLICEL_FFY
  • CE=434
  • CK=443
  • D=443
  • Q=443
  • SR=443
SLICEL_G
  • A1=498
  • A2=444
  • A3=64
  • A4=22
  • D=498
SLICEL_XORF
  • 0=416
  • 1=416
  • O=416
SLICEL_XORG
  • 0=416
  • 1=416
  • O=416
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s4000-fg676-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s4000-fg676-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
XSLTProcess 1 1 0 0 0 0 0
_impact 8 7 0 0 0 0 0
bitgen 6 6 0 0 0 0 0
cpldfit 1 1 0 0 0 0 0
hprep6 1 1 0 0 0 0 0
map 5 5 0 0 0 0 0
ngdbuild 6 6 0 0 0 0 0
par 5 5 0 0 0 0 0
taengine 1 1 0 0 0 0 0
trce 5 5 0 0 0 0 0
tsim 1 1 0 0 0 0 0
xst 5 5 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/cpld_all/libs_le_cb16ce.htm ( 1 ) /doc/usenglish/isehelp/cpld_all/libs_le_d3_8e.htm ( 1 )
/doc/usenglish/isehelp/cpld_all/libs_le_fdcp.htm ( 1 ) /doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 )
/doc/usenglish/isehelp/spartan3a/libs_le_fd8ce.htm ( 1 )
 
Project Statistics
PROP_CompxlibOverwriteLib=true PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PostTrceFastPath=false PROP_PreTrceFastPath=false
PROP_PrecVhdlSyntax=VHDL 93 PROP_PropSpecInProjFile=Store all values
PROP_SimModelInsertBuffersPulseSwallow=false PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_XPowerOptLoadXMLFile=changed PROP_XPowerOptOutputFile=changed
PROP_intProjectCreationTimestamp=2015-08-12T12:59:39 PROP_intWbtProjectID=BA466B1531AB2551D295982D279652AA
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_xilxSynthKeepHierarchy=Yes
PROP_xilxSynthRegDuplication=false PROP_xstEquivRegRemoval=false
PROP_xstSliceUtilRatio=97 PROP_AutoTop=true
PROP_CompxlibSmartModels=true PROP_DevFamily=Spartan3
PROP_MapEffortLevel=Standard PROP_vsim_otherCmdLineOptions=-novopt
PROP_CompxlibSimPath=changed PROP_DevDevice=xc3s4000
PROP_DevFamilyPMName=spartan3 PROP_DevPackage=fg676
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=18
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUF=3 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=17 NGDBUILD_NUM_FDCE=848
NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_FDPE=15 NGDBUILD_NUM_GND=9 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT2=851 NGDBUILD_NUM_LUT2_D=1 NGDBUILD_NUM_LUT3=83
NGDBUILD_NUM_LUT3_L=9 NGDBUILD_NUM_LUT4=44 NGDBUILD_NUM_LUT4_L=4 NGDBUILD_NUM_MUXCY=824
NGDBUILD_NUM_MUXF5=27 NGDBUILD_NUM_MUXF6=8 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_XORCY=832
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUF=3 NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=17 NGDBUILD_NUM_FDCE=848
NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_FDPE=15 NGDBUILD_NUM_GND=9 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT2=851 NGDBUILD_NUM_LUT2_D=1
NGDBUILD_NUM_LUT3=83 NGDBUILD_NUM_LUT3_L=9 NGDBUILD_NUM_LUT4=44 NGDBUILD_NUM_LUT4_L=4
NGDBUILD_NUM_MUXCY=824 NGDBUILD_NUM_MUXF5=27 NGDBUILD_NUM_MUXF6=8 NGDBUILD_NUM_OBUF=1
NGDBUILD_NUM_XORCY=832
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s4000-5-fg676 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=Yes -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=97 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=NO -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=NO
-slice_utilization_ratio_maxmargin=5