top_level Project Status
Project File:	test0.xise	Parser Errors:
Module Name:	top_level	Implementation State:	New
Target Device:	xc9572xl-5VQ44	Errors:
Product Version:	ISE 14.7	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
CPLD Fitter Report (Text)
Power Report

 

Secondary Reports			[-]
Report Name	Status	Generated
Post-Fit Simulation Model Report

Date Generated: 08/24/2020 - 15:51:36