System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
LD_LIBRARY_PATH /opt/Xilinx/14.3/ISE_DS/ISE//lib/lin:
/opt/Xilinx/14.3/ISE_DS/ISE/lib/lin:
/opt/Xilinx/14.3/ISE_DS/ISE/smartmodel/lin/installed_lin/lib:
/opt/Xilinx/14.3/ISE_DS/ISE/sysgen/lib:
/opt/Xilinx/14.3/ISE_DS/EDK/lib/lin:
/opt/Xilinx/14.3/ISE_DS/common/lib/lin
< data not available > < data not available > < data not available >
LMC_HOME /opt/Xilinx/14.3/ISE_DS/ISE/smartmodel/lin/installed_lin < data not available > < data not available > < data not available >
PATH /opt/Xilinx/14.3/ISE_DS/ISE//bin/lin:
/opt/Xilinx/14.3/ISE_DS/../../Vivado_HLS/2012.3/bin:
/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin:
/opt/Xilinx/14.3/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.3/ISE_DS/ISE/sysgen/bin:
/opt/Xilinx/14.3/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.3/ISE_DS/../../Vivado/2012.3/bin:
/opt/Xilinx/14.3/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.3/ISE_DS/EDK/bin/lin:
/opt/Xilinx/14.3/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.3/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.3/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.3/ISE_DS/common/bin/lin:
/usr/lib/lightdm/lightdm:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games
< data not available > < data not available > < data not available >
XILINX /opt/Xilinx/14.3/ISE_DS/ISE/ < data not available > < data not available > < data not available >
XILINXD_LICENSE_FILE 2100@ouse.ad.cs.york.ac.uk < data not available > < data not available > < data not available >
XILINX_DSP /opt/Xilinx/14.3/ISE_DS/ISE < data not available > < data not available > < data not available >
XILINX_EDK /opt/Xilinx/14.3/ISE_DS/EDK < data not available > < data not available > < data not available >
XILINX_PLANAHEAD /opt/Xilinx/14.3/ISE_DS/PlanAhead < data not available > < data not available > < data not available >
XILINX_VIVADO /opt/Xilinx/14.3/ISE_DS/../../Vivado/2012.3 < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   ALU.prj  
-ifmt   mixed MIXED
-ofn   ALU  
-ofmt   NGC NGC
-p   xc3s400-5-pq208  
-top   ALU  
-opt_mode Optimization Goal Speed SPEED
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized as_optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets ALLCLOCKNETS
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-mult_style   Auto AUTO
-iobuf   YES YES
-max_fanout   100000 500
-bufg   8 8
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Yes YES
-use_sync_set   Yes YES
-use_sync_reset   Yes YES
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU T9550 @ 2.66GHz/2661.000 MHz <  data not available  > <  data not available  > <  data not available  >
Host mike-TECRA-A10 <  data not available  > <  data not available  > <  data not available  >
OS Name Ubuntu <  data not available  > <  data not available  > <  data not available  >
OS Release Ubuntu 12.04.5 LTS <  data not available  > <  data not available  > <  data not available  >