RING_COUNTER_3 Project Status (03/13/2025 - 21:03:04) | |||
Project File: | counter.xise | Parser Errors: | No Errors |
Module Name: | COUNTER_8 | Implementation State: | Synthesized |
Target Device: | xc7a100t-3csg324 |
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No Errors |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 8 | 126800 | 0% | |
Number of Slice LUTs | 9 | 63400 | 0% | |
Number of fully used LUT-FF pairs | 8 | 9 | 88% | |
Number of bonded IOBs | 20 | 210 | 9% | |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu Mar 13 21:03:04 2025 | 0 | 0 | 0 | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Thu Mar 13 21:02:29 2025 |