RING_COUNTER_3 Project Status (03/13/2025 - 21:03:04)
Project File: counter.xise Parser Errors: No Errors
Module Name: RING_COUNTER_3 Implementation State: Synthesized
Target Device: xc7a100t-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 3 126800 0%
Number of fully used LUT-FF pairs 0 3 0%
Number of bonded IOBs 5 210 2%
Number of BUFG/BUFGCTRLs 1 32 3%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Mar 13 20:34:58 2025   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu Mar 13 21:02:29 2025

Date Generated: 03/13/2025 - 21:03:04