NOR_8 Project Status (03/13/2025 - 21:09:49) | |||
Project File: | nor_8_gate.xise | Parser Errors: | No Errors |
Module Name: | NOR_8 | Implementation State: | Synthesized |
Target Device: | xc7a100t-3csg324 |
|
No Errors |
Product Version: | ISE 14.7 |
|
No Warnings |
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice LUTs | 2 | 63400 | 0% | |
Number of fully used LUT-FF pairs | 0 | 2 | 0% | |
Number of bonded IOBs | 9 | 210 | 4% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu Mar 13 21:09:48 2025 | 0 | 0 | 0 | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |