A summary of documents taken from SimpleCPU lectures, practicals and web pages, please refer back to these for more detailed information / explanation: (Link).
Figure 1 : SimpleCPU_v1d block diagram
This processor uses a fixed length 16bit instruction format. Memory is 4096 x 16bit, allowing an instruction to be stored in a single memory location. On reset the first instruction is fetched from address 0. The data processing unit i.e. ALU, is 16bit wide. The register file contains 8 x 16bit general purpose registers: RA - RH. The CALL-RET stack is implemented in external memory, accessed via the stack pointer (SP) register. Push / Pop instruction can be used to pass parameter and results between subroutines / main program. If stack frames are used the general purpose register RH should be reserved as the frame pointer. This processor supports interrupts. Multiple levels of interrupts are supported using an external interrupt controller. The interrupt vector address is defined as a constant within the ISE schematic and may be changed by the user. The interrupt return address is automatically stored on the CALL-RET stack, however, the user is responsible for check-pointing / restoring any registers used by the interrupt service routine (ISR). To simplify the hardware implementation this CPU has separate 16bit data-in and data-out buses. This processor does not support byte addressable memory.
Figure 2 : SimpleCPU_v1d instruction formats
Figure 3 : status register, flags.
Figure 4 : instruction formats
Example : move RA 1 Addressing mode : immediate Opcode : 0000 RTL : RX <- ( (K7)8 || KK ) Flags set : None
Move signed 8bit value into general purpose register. The bit field KK is as defined in figure 2. In this example RX is register RA and KK is the value 1, signed extended to 16bits. Therefore, at the end of the execution phase the register RA=1.
Example : add RB 2 Addressing mode : immediate Opcode : 0001 RTL : RX <- RX + ( (K7)8 || KK ) Flags set : Z,C,O,P,N
Add signed 8bit value to general purpose register. The bit field KK is as defined in figure 2. In this example RX is register RB and KK is the value 2, signed extended to 16bits. Therefore, if RB=1 at the end of the execution phase register RB=3.
Example : sub RC 33 Addressing mode : immediate Opcode : 0010 RTL : RX <- RX - ( (K7)8 || KK ) Flags set : Z,C,O,P,N
Subtract signed 8bit value from general purpose register. The bit field KK is as defined in figure 2. In this example RX is register RC and KK is the value 3, signed extended to 16bits. Therefore, if RC=5 at the end of the execution phase register RC=2.
Example : and RD 4 Addressing mode : immediate Opcode : 0011 RTL : RX <- RX & ( (0)8 || KK ) Flags set : Z,C,O,P,N
Perform 8bit bitwise AND on general purpose register. The bit field KK is as defined in figure 2. In this example RX is register RD and KK is the value 4. Therefore, if RD=7 at the end of the execution phase register RD=4. Note, as the value KK represents a binary pattern this data is not sign extended.
Example : load RA 123 Addressing mode : absolute Opcode : 0100 RTL : RA <- M[AAA] Flags set : None
Transfer a 16bit value from memory to general purpose register RA. The bit field AAA is as defined in figure 2. In this example AAA is the address 123, therefore, if M[123]=10 at the end of the execution phase register RA=10. Note, the destination register is hardwired to register RA, you can not use other registers.
Example : store RA 234 Addressing mode : absolute Opcode : 0101 RTL : M[AAA] <- RA Flags set : None
Store 16bit value in general purpose register RA to memory. The bit field AAA is as defined in figure 2. In this example AAA is the address 234, therefore, if RA=9 at the end of the execution phase memory location M[234]=9. Note, the source register is hardwired to register RA, you can not use other registers.
Example : addm RA 345 Addressing mode : absolute Opcode : 0110 RTL : RA <- RA + M[AAA] Flags set : Z,C,O,P,N
Add 16bit value stored in memory to general purpose register RA. The bit field AAA is as defined in figure 2. In this example AAA is the address 345, therefore, if RA=20 and M[345]=10 at the end of the execution phase register RA=30. Note, the destination register is hardwired to register RA, you can not use other registers.
Example : subm RA 456 Addressing mode : absolute Opcode : 0111 RTL : RA <- RA - M[AAA] Flags set : Z,C,O,P,N
Subtract 16bit value stored in memory from general purpose register RA. The bit field AAA is as defined in figure 2. In this example AAA is the address 456, therefore, if RA=20 and M[456]=10 at the end of the execution phase register RA=10. Note, the destination register is hardwired to register RA, you can not use other registers.
Example : jump 200 Addressing mode : direct Opcode : 1000 RTL : PC <- AAA Flags set : None
Unconditional jump. The bit field AAA is as defined in figure 2. In this example AAA is the address 200, at the end of the execution phase the PC is updated to 200.
Example : jumpz 201 Addressing mode : direct Opcode : 1001 RTL : IF Z=1 THEN PC <- AAA ELSE PC <- PC + 1 Flags set : None
Jump if last arithmetic or logical instruction produced a zero result i.e. jump is conditional on the status register’s Z flag. The bit field AAA is as defined in figure 2. In this example AAA is the address 201, if Z=1 the PC is set to the value 201 at the end of the execution phase, else PC+1. Note, status register (Z flag) is only updated by arithmetic or logical functions.
Example : jumpnz 202 Addressing mode : direct Opcode : 1010 RTL : IF Z=0 THEN PC <- AAA ELSE PC <- PC + 1 Flags set : None
Jump if last arithmetic or logic instruction did not produce a zero result i.e. jump is conditional on the status register’s Z flag. The bit field AAA is as defined in figure 2. In this example AAA is the address 202, if Z=0 the PC is set to the value 202 at the end of the execution phase, else PC+1. Note, status register (Z flag) is only updated by arithmetic or logical functions.
Example : jumpc 203 Addressing mode : direct Opcode : 1011 RTL : IF C=1 THEN PC <- AAA ELSE PC <- PC + 1 Flags set : None
Jump if last arithmetic instruction generated a carry i.e. jump is conditional on the status register’s C flag. The bit field AAA is as defined in figure 2. In this example AAA is the address 203, if C=1 the PC is set to the value 203 at the end of the execution phase, else PC+1. Note, status register (C flag) is only updated by arithmetic functions.
Example : call 300
Addressing mode : direct
Opcode : 1100
RTL : STACK[SP]<- PC + 1
: SP <- SP + 1
: PC <- AAA
Flags set : None
Call subroutine. The bit field AAA is as defined in figure 2. In this example AAA is the address 300, at the end of the execution phase the PC is updated to 300. Note, CALL-RET stack memory is implemented in a separate memory space i.e. LIFO buffer, with integrated stack pointer (SP), max depth of 4.
Example : ret
Addressing mode : direct
Opcode : 1111 + 0000
RTL : SP <- SP - 1
: PC <- STACK[SP]
Flags set : None
Return from subroutine. At the end of the execution phase the PC will be updated to the value on the top of the CALL-RET stack. Note, CALL-RET stack memory is implemented in a separate memory space i.e. LIFO buffer, with integrated stack pointer (SP), max depth of 4.
Example : move ra rb Addressing mode : register Opcode : 1111 + 0001 RTL : RX <- RY Flags set : None
Transfer a 16bit value from source to destination general purpose register. Higher and lower opcode values as defined in figure 2. In this example RX is register RA and RY is register RB, therefore, if RB=1 and RA=100 at the end of the execution phase register RA=1.
Example : load ra (rb) Addressing mode : register indirect Opcode : 1111 + 0010 RTL : RX <- M[RY] Flags set : None
Transfer a 16bit value from memory to destination general purpose register. Accessed memory address stored in register enclosed by brackets. Higher and lower opcode values as defined in figure 2. In this example RX is register RA and RY is register RB, therefore, if RB=100 and M[100]=5 at the end of the execution phase register RA=5.
Example : store rb (rc) Addressing mode : register indirect Opcode : 1111 + 0011 RTL : M[RY] <- RX Flags set : None
Transfer a 16bit value from general purpose register to memory. Accessed memory address stored in register enclosed by brackets. Higher and lower opcode values as defined in figure 2. In this example RX is register RB and RY is register RC, therefore, if RB=10 and RC=100 at the end of the execution phase memory location M[100]=10.
Example : rol rb Addressing mode : register Opcode : 1111 + 0100 RTL : RX <- ( RX(14:0) || RX(15) ) Flags set : Z,C,O,P,N
Rotate bits within general purpose register one position to the left. Higher and lower opcode values as defined in figure 2. In this example RX is register RB, therefore, if RB=2 at the end of the execution phase register RB=4.
Example : xor ra rb Addressing mode : register Opcode : 1111 + 1010 RTL : RX <- RX + RY Flags set : Z,C,O,P,N
Perform bitwise XOR on 16bit source and destination general purpose registers. Higher and lower opcode values as defined in figure 2. In this example RX is register RA and RY is register RB, therefore, if RA=7 and RB=2 at the end of the execution phase register RA=5.
IMPORTANT: the instructions below have not been implemented in the base simpleCPUv1d system. However, these instruction can be added to the system if required.
Example : or ra 10 Addressing mode : immediate Opcode : 1101 RTL : RX <- RX | ( (0)8 || KK ) Flags set : Z,C,O,P,N
Perform 8bit bitwise OR on general purpose register. Not implemented. The bit field KK is as defined in figure 2. In this example RX is register RA and KK is the value 10, therefore, if RA=7 at the end of the execution phase register RA=15. Note, as the value KK represents a binary pattern this data is not sign extended.
Example : xop1 rb 1 Addressing mode : immediate Opcode : 1110 RTL : undefined Flags set : undefined
This instruction’s function is not defined, therefore, it may be modified to suit processing requirements. However, this functionality is limited by the ALU’s hardware and the instruction format as implemented in the assembler. Not implemented.
Example : ror rb Addressing mode : register Opcode : 1111 + 0101 RTL : RX <- ( RX(0) || RX(15:1) ) Flags set : Z,C,O,P,N
Rotate bits within general purpose register one position to the right. Not implemented. Higher and lower opcode values as defined in figure 2. In this example RX is register RB, therefore, if RB=8 at the end of the execution phase register RB=4.
Example : add ra rb Addressing mode : register Opcode : 1111 + 0110 RTL : RX <- RX + RY Flags set : Z,C,O,P,N
Add 16bit source general purpose register to destination general purpose register. Not implemented. Higher and lower opcode values as defined in figure 2. In this example RX is register RA and RY is register RB, therefore, if RA=20 and RB=10 at the end of the execution phase register RA=30.
Example : sub ra rb Addressing mode : register Opcode : 1111 + 0111 RTL : RX <- RX - RY Flags set : Z,C,O,P,N
Subtract 16bit source general purpose register from destination general purpose register. Not implemented. Higher and lower opcode values as defined in figure 2. In this example RX is register RA and RY is register RB, therefore, if RA=25 and RB=10 at the end of the execution phase register RA=15.
Example : and ra rb Addressing mode : register Opcode : 1111 + 1000 RTL : RX <- RX & RY Flags set : Z,C,O,P,N
Perform bitwise AND on 16bit source and destination general purpose registers. Not implemented. Higher and lower opcode values as defined in figure 2. In this example RX is register RA and RY is register RB, therefore, if RA=15 and RB=7 at the end of the execution phase register RA=7.
Example : or ra rb Addressing mode : register Opcode : 1111 + 1001 RTL : RX <- RX | RY Flags set : Z,C,O,P,N
Perform bitwise OR on 16bit source and destination general purpose registers. Not implemented. Higher and lower opcode values as defined in figure 2. In this example RX is register RA and RY is register RB, therefore, if RA=15 and RB=7 at the end of the execution phase register RA=15.
Example : asl rb Addressing mode : register Opcode : 1111 + 1011 RTL : RX <- ( RX(14:0) || 0 ) Flags set : Z,C,O,P,N
Arithmetic shift left, shift bits in general purpose register one position to the left inserting 0 into LSB. Not implemented. Higher and lower opcode values as defined in figure 2. In this example RX is register RB, therefore, if RB=10 at the end of the execution phase register RB=20.
Example : xop2 ra (rb) Addressing mode : register indirect Opcode : 1111 + 1100 RTL : undefined Flags set : undefined
This instruction’s function is not defined, therefore, it may be modified to suit processing requirements. However, this functionality is limited by the ALU’s hardware and the instruction format as implemented in the assembler. Not implemented.
Example : xop3 ra rb Addressing mode : register Opcode : 1111 + 1101 RTL : undefined Flags set : undefined
This instruction’s function is not defined, therefore, it may be modified to suit processing requirements. However, this functionality is limited by the ALU’s hardware and the instruction format as implemented in the assembler. Not implemented.
Example : xop2 ra (rb) Addressing mode : register indirect Opcode : 1111 + 1110 RTL : undefined Flags set : undefined
This instruction’s function is not defined, therefore, it may be modified to suit processing requirements. However, this functionality is limited by the ALU’s hardware and the instruction format as implemented in the assembler. Not implemented.
Example : xop3 ra rb Addressing mode : register Opcode : 1111 + 1111 RTL : undefined Flags set : undefined
This instruction’s function is not defined, therefore, it may be modified to suit processing requirements. However, this functionality is limited by the ALU’s hardware and the instruction format as implemented in the assembler. Not implemented.
Pseudo Code Assembler code Notes
IF A=0 start: variable A is stored in register
THEN and RA 0xFF RA and is 8bits. Variable B is
B = 10 jumpz zero stored in RB and is 8bits.
ELSE notZero:
B = 20 move rb 20
END IF jump exit
zero:
move rb 10
exit:
jump exit
Pseudo Code Assembler code Notes
IF A=B start: variable A is stored in register
THEN subm RA 100 RA, variable B is stored in M[100]
C = 10 jumpz equal and variable C is stored in M[101]
ELSE notEqual:
C = 20 move RA 20
END IF store RA 101
jump exit
equal:
move RA 10
store RA 101
exit:
jump exit
Pseudo Code Assembler code Notes
IF A<B start: variable A is stored in register
THEN subm RA 100 RA, variable B is stored in M[100]
C = 10 rol RA and variable C is stored in M[101]
ELSE and RA 0x1
C = 20 jumpnz less
END IF greater:
move RA 10
store RA 101
jump exit
less:
move RA 20
store RA 101
exit:
jump exit
Pseudo Code Assembler code Notes
FOR I in {0..4} start: variable I is stored in
DO move RD 4 register RD and variable A
A = A + 1 move RA 0 in register RA. Loop count is
DONE loop: an 8bit value.
and RD 0xFF
jumpz exit
add RA 1
sub RD 1
jump loop
exit:
jump exit
Pseudo Code Assembler code Notes
WHILE (A<10) start: variable RA stored in register
DO move RA 0 RA and is an 8bit value.
A = A + 1 loop:
DONE move RB RA
sub RB 10
jumpz exit
add RA 1
jump loop
exit:
jump exit
Pseudo Code Assembler code Notes
A = 100 start: move instruction limited to a
B = 1000 move RA 0x64 signed 8bit value. Variables A
C = 10000 move RB 0x3E and B are stored in registers
D = 65535 rol RB RA and RB. Variables C and D
rol RB stored in memory.
rol RB
rol RB
add RB 8
move RC 0x27
rol RC
rol RC
rol RC
rol RC
rol RC
rol RC
rol RC
rol RC
add RC 0x10
store RC C
exit:
jump exit
C:
.data 0
D:
.data 0xFFFF
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Contact email: mike@simplecpudesign.com