Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version1577090
date_generatedTue Nov 28 12:38:38 2017 os_platformLIN64
product_versionVivado v2016.2 (64-bit) project_id4b4c401b3f814755b1f4dbcc306d8de5
project_iteration2 random_id7053d85f-fa28-4818-9213-d4fa244e0474
registration_id7053d85f-fa28-4818-9213-d4fa244e0474 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecsg324 target_speed-3
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-4720HQ CPU @ 2.60GHz cpu_speed3400.007 MHz
os_nameUbuntu os_releaseUbuntu 14.04.5 LTS
system_ram8.000 GB total_processors1

vivado_usage
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_2 currentsynthesisrun=synth_2
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=68 simulator_language=Mixed srcsetcount=12 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=2 carry4=4 fdce=83 gnd=2
ibuf=6 lut1=2 lut2=6 lut3=4
lut4=19 lut5=34 lut6=27 obuf=32
ramb18e1=1 vcc=3
pre_unisim_transformation
bufg=2 carry4=4 fdce=83 gnd=2
ibuf=6 lut1=2 lut2=6 lut3=4
lut4=19 lut5=34 lut6=27 obuf=32
ramb18e1=1 vcc=3

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=2 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=83 srls_augmented=0
srls_newly_gated=0 srls_total=0

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified]
results
cfgbvs-1=1 reqp-1840=34

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0.5 block_ram_tile_util_percentage=1.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=1 ramb18_util_percentage=1.00
ramb18e1_only_used=1 ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=2 carry4_functional_category=CarryLogic carry4_used=4
fdce_functional_category=Flop & Latch fdce_used=83 ibuf_functional_category=IO ibuf_used=6
lut1_functional_category=LUT lut1_used=2 lut2_functional_category=LUT lut2_used=6
lut3_functional_category=LUT lut3_used=4 lut4_functional_category=LUT lut4_used=19
lut5_functional_category=LUT lut5_used=34 lut6_functional_category=LUT lut6_used=27
obuf_functional_category=IO obuf_used=32 ramb18e1_functional_category=Block Memory ramb18e1_used=1
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=92 lut_as_logic_util_percentage=0.44
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=83 register_as_flip_flop_util_percentage=0.20
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=92 slice_luts_util_percentage=0.44
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=83 slice_registers_util_percentage=0.20
fully_used_lut_ff_pairs_fixed=0.20 fully_used_lut_ff_pairs_used=0 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=92 lut_as_logic_util_percentage=0.44
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=27
lut_ff_pairs_with_one_unused_lut_fixed=27 lut_ff_pairs_with_one_unused_lut_used=27 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=27 lut_flip_flop_pairs_util_percentage=0.13 slice_available=8150 slice_fixed=0
slice_used=31 slice_util_percentage=0.38 slicel_fixed=0 slicel_used=22
slicem_fixed=0 slicem_used=9 unique_control_sets_used=8 using_o5_and_o6_fixed=8
using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=92
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=292593 bogomips=5187 bram18=1 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=8
dsp=0 effort=2 estimated_expansions=232050 ff=83
global_clocks=2 high_fanout_nets=0 iob=38 lut=92
movable_instances=225 nets=257 pins=1214 pll=0
router_runtime=11.270000 router_timing_driven=1 threads=8 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=[specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=-4
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=[specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcsg324-3
-resource_sharing=off -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -shreg_min_size=default::3 -top=mcp_top_level
-verilog_define=default::[not_specified]
usage
elapsed=00:00:18s hls_ip=0 memory_gain=472.129MB memory_peak=1435.746MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::